The present invention is directed generally to phase locked loops (PLL) and delay locked loops (DLL) and, more particularly, to locked loops having a digital phase mixer.
PLLs and DLLs are often used as synchronization circuits for generating clock signals for compensating for a skew between an external clock signal and data or between the external clock signal and an internal clock signal.
FIG. 1 is an example of a block diagram illustrating a prior art clock synchronization circuit 10, which is a linear, register controlled DLL suitable for use in a semiconductor memory device. The DLL 10 includes: a receiving circuit 11 which produces a buffered clock signal Iclk. A variable delay line 12 and a phase detector 13 are responsive to the receiving circuit 11. The phase detector 13 produces shift left (SHL) and shift right (SHR) control signals which are input to a shift register 14. The shift register 14 produces control signals CSL1-CSLn which are used to control the variable delay line 12. The signals SHL and SHR are also input to a control unit 15 which produces a signal CON input to the shift register 14 and signals SN and SA which are input to a phase mixer 16. The phase mixer 16 also receives signals NDS and ADS from the variable delay line 12. The NDS signal is produced by delaying the buffered clock signal Iclk for a predetermined time, and the ADS clock signal is produced by additionally delaying the normal delay clock signal NDS for a further predetermined time.
The phase mixer 16 mixes the phases of the normal delay clock signal NDS and the additionally delayed clock signal ADS from the variable delay line 12, and outputs an internal clock signal INclk having a phase that is between the phases of the two input clock signals. The internal clock signal INclk is feedback through a delay monitor 17 to the phase detector 13. The control unit 15 outputs the control signals SN1-SNn and SA1-SAn to control the operation of the phase mixer 16 so that the internal clock signal INclk has a phase that is between the phases of the normal delay clock signal NDS and the additionally delayed clock signal ADS.
FIG. 2 is an example of a detailed circuit diagram illustrating a prior art delay line 19 constructed of four conventional delay elements 20-23. Each of the delay elements 20-23 is comprised of two series connected NAND gates. A clock signal ClkO is available at the output of the delay element 20. A clock signal Clk 1 is available at the output of delay element 21. A clock signal Clk2 is available at the output of delay element 22 and a clock signal CLKout is available at the output of the delay element 23. The delay line 19 of FIG. 2 may be used in conjunction with the conventional six-weight phase mixers 25 and 26 as shown in FIG. 3 for even and odd delay lines, respectively.
Turning now to FIG. 3, FIG. 3 illustrates two conventional six weight phase mixers 25, 26 along with input buffers 27. The input buffers 27 provide two clock signals which are input to the conventional six-weight phase mixers 25, 26. The phase mixers receive (r−1) bit Q<0:r> that determines the weight to be assigned to each of the input clock signals. The output delay/slew rate of the phase mixers is generally controlled by Q<0:r> through the use of thermometer codes and the capacitive load of the components connected to and used in constructing the phase mixers.
FIG. 4 illustrates one inverter 32 and two unit digital phase mixers 30, 31, which comprise a two weight (two-bit) phase mixer 29. The two weight phase mixer 29 is sometimes referred to as a cell. The cell shown in FIG. 4 is often fabricated in pairs to allow options for the number of delays and to allow the layout to share common inputs. The conventional six-weight phase mixers 25 and 26 can be constructed from cells which are the same as that shown in FIG. 4.
Each of the unit phase mixers 30, 31 may have a construction as shown in FIG. 5. FIG. 5 is an example of a prior art, unit (one-bit) phase mixer labeled 30 or 31. Any number of unit phase mixers 30/31 may be connected in parallel as shown, for example, in FIG. 6 which illustrates a six weight phase mixer 34.
Note that in FIG. 6, one input (early_in) to the early unit phase mixers 62 will lag the other input (late_in) to the late unit phase mixers 63. As a result, there is a short timing gap (tg) between the two inputs. FIGS. 6A and 6B show the input (early_in) to the early unit phase mixers and the input (late_in) to the late unit phase mixers, and the timing gap (tg) between the two inputs. FIGS. 6C-6E illustrate output signals produced by the six weight phase mixer under various weighting conditions. The timing gap (tg) between the early input to the early unit phase mixers and the late input to the late unit phase mixers creates a fighting condition that causes short circuit currents to flow between the early unit phase mixers and late unit phase mixers. In this example, the worst case fighting condition occurs during time interval (tg), while Q<0:5> equal is to 000111 or 111000. Moreover, notice that in the prior art, the fighting condition exists at any Q<0:5> except only two cases (000000 and 111111). Thus, it is desirable to have a phase mixer that reduces or eliminates this fighting condition while maintaining or improving reliability, power dissipation, and a wide frequency range of operation.